Full list of Xilinx FPGA & CPLD, Xilinx Spartan and Spartan-XL Families , Xilinx Virtex 2.5 V FPGA ,Xilinx CoolRunner-II CPLD



Xilinx XC3000 Series FPGA

 (XC3000A/L, XC3100A/L)

 

Features

• Complete line of four related Field Programmable Gate

Array product families

- XC3000A, XC3000L, XC3100A, XC3100L

• Ideal for a wide range of custom VLSI design tasks

- Replaces TTL, MSI, and other PLD logic

- Integrates complete sub-systems into a single

package

- Avoids the NRE, time delay, and risk of conventional

masked gate arrays

• High-performance CMOS static memory technology

- Guaranteed toggle rates of 70 to 370 MHz, logic

delays from 7 to 1.5 ns

- System clock speeds over 85 MHz

- Low quiescent and active power consumption

• Flexible FPGA architecture

- Compatible arrays ranging from 1,000 to 7,500 gate

complexity

- Extensive register, combinatorial, and I/O

capabilities

- High fan-out signal distribution, low-skew clock nets

- Internal 3-state bus capabilities

- TTL or CMOS input thresholds

- On-chip crystal oscillator amplifier

• Unlimited reprogrammability

- Easy design iteration

- In-system logic changes

• Extensive packaging options

- Over 20 different packages

- Plastic and ceramic surface-mount and pin-grid-

array packages

- Thin and Very Thin Quad Flat Pack (TQFP and

VQFP) options

• Complete Development System

- Schematic capture, automatic place and route

- Logic and timing simulation

- Interactive design editor for design optimization

- Timing calculator

- Interfaces to popular design environments like

Viewlogic, Cadence, Mentor Graphics, and others

 

7Additional XC3100A Features

• Ultra-high-speed FPGA family with six members

- 50-85 MHz system clock rates

- 190 to 370 MHz guaranteed flip-flop toggle rates

- 1.55 to 4.1 ns logic delays

• High-end additional family member in the 22 X 22 CLB

array-size XC3195A device

• 8 mA output sink current and 8 mA source current

• Maximum power-down and quiescent current is 5 mA

• 100% architecture and pin-out compatible with other

XC3000 families

• Software and bitstream compatible with the XC3000,

XC3000A, and XC3000L families

XC3100A combines the features of the XC3000A and

XC3100 families:

• Additional interconnect resources for TBUFs and CE

inputs

• Error checking of the configuration bitstream

• Soft startup holds all outputs slew-rate limited during

initial power-up

More advanced CMOS process

       

 Simple overview of those XC3000 products

   

• XC3000A Family — The XC3000A is an enhanced

version of the basic XC3000 family, featuring additional interconnect resources and other user-friendly enhancements.

• XC3000L Family — The XC3000L is identical in

architecture and features to the XC3000A family, but

operates at a nominal supply voltage of 3.3 V. The

XC3000L is the right solution for battery-operated and  low-power applications.

 

• XC3100A Family — The XC3100A is a

performance-optimized relative of the XC3000A family. While both families are bitstream and footprint compatible, the XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The XC3100A family also offers one additional array size, the XC3195A.

• XC3100L Family — The XC3100L is identical in

architectures and features to the XC3100A family, but operates at a nominal supply voltage of 3.3V.

 

 

Xilinx XC5200 Series FPGA

 Features

• Low-cost, register/latch rich, SRAM based

reprogrammable architecture

- 0.5mm three-layer metal CMOS process technology

- 256 to 1936 logic cells (3,000 to 23,000 “gates”)

- Price competitive with Gate Arrays

• System Level Features

- System performance beyond 50 MHz

- 6 levels of interconnect hierarchy

- VersaRing™ I/O Interface for pin-locking

- Dedicated carry logic for high-speed arithmetic

functions

- Cascade chain for wide input functions

- Built-in IEEE 1149.1 JTAG boundary scan test

circuitry on all I/O pins

- Internal 3-state bussing capability

- Four dedicated low-skew clock or signal distribution

nets

• Versatile I/O and Packaging

- Innovative VersaRing™ I/O interface provides a high

logic cell to I/O ratio, with up to 244 I/O signals

- Programmable output slew-rate control maximizes

performance and reduces noise

- Zero Flip-Flop hold time for input registers simplifies

system timing

- Independent Output Enables for external bussing

- Footprint compatibility in common packages within

the XC5200 Series and with the XC4000 Series

- Over 150 device/package combinations, including

advanced BGA, TQ, and VQ packaging available

• Fully Supported by Xilinx Development System

- Automatic place and route software

- Wide selection of PC and Workstation platforms

- Over 100 3rd-party Alliance interfaces

- Supported by shrink-wrap Foundation software

     

  Xilinx XC4000XLA/XV FPGA

 

XC4000XLA/XV Family Features

• System-featured Field-Programmable Gate Arrays

- Select-RAMTM memory: on-chip ultra-fast RAM with

- Synchronous write option

- Dual-port RAM option

- Flexible function generators and abundant flip-flops

- Dedicated high-speed carry logic

- Internal 3-state bus capability

- Eight global low-skew clock or signal distribution

networks

• Flexible Array Architecture

• Low-power Segmented Routing Architecture

• Systems-oriented Features

- IEEE 1149.1-compatible boundary scan

- Individually programmable output slew rate

- Programmable input pull-up or pull-down resistors

- Unlimited reprogrammability

• Read Back Capability

- Program verification and internal node observability

Electrical Features

• XLA Devices Require 3.0 - 3.6 V (VCC)

• XV Devices Require 2.3- 2.7 V (VCCINT)

and 3.0 - 3.6 V (VCCIO)

• 5.0 V TTL compatible I/O

• 3.3 V LVTTL, LVCMOS compliant I/O

• 5.0 V and 3.0 V PCI Compliant I/O

• 12 mA or 24 mA Current Sink Capability

• Safe under All Power-up Sequences

• XLA Consumes 40% Less Power than XL

• XV Consumes 65% Less Power than XL

• Optional Input Clamping to VCC (XLA) or VCCIO (XV)

 

Additional Features

• Footprint Compatible with XC4000XL FPGAs - Lower

cost with improved performance and lower power

• Advanced Technology — 5 layer metal, 0.25 mm CMOS

process (XV) or 0.35 mm CMOS process (XLA)

• Highest Performance — System erformance beyond

100 MHz

• High Capacity — Up to 500,000 system gates and

270,000 synchronous SRAM bits

• Low Power — 3.3 V/2.5 V technology plus segmented

routing architecture

• Safe and Easy to Use — Interfaces to any combination

of 3.3 V and 5.0 V TTL compatible devices

 

     

  Xilinx Spartan and Spartan-XL Families

FPGA

 

Spartan and Spartan-XL Features

 

advanced members for the Spartan Series.

• First ASIC replacement FPGA for high-volume

production with on-chip RAM

• Density up to 1862 logic cells or 40,000 system gates

• Streamlined feature set based on XC4000 architecture

• System performance beyond 80 MHz

• Broad set of AllianceCORE™ and LogiCORE™

predefined solutions available

• Unlimited reprogrammability

• Low cost

• System level features

- Available in both 5V and 3.3V versions

- On-chip SelectRAM™ memory

- Fully PCI compliant

- Full readback capability for program verification

and internal node observability

- Dedicated high-speed carry logic

- Internal 3-state bus capability

- Eight global low-skew clock or signal networks

- IEEE 1149.1-compatible Boundary Scan logic

- Low cost plastic packages available in all densities

- Footprint compatibility in common packages

• Fully supported by powerful Xilinx development system

- ISE Foundation Series: Integrated, shrink-wrap

software

- ISE Alliance Series: Dozens of PC and workstation

third party development systems supported

- Fully automatic mapping, placement and routing

   

Additional Spartan-XL Features

• 3.3V supply for low power with 5V tolerant I/Os

• Power down input

• Higher performance

• Faster carry logic

• More flexible high-speed clock network

• Latch capability in Configurable Logic Blocks

• Input fast capture latch

• Optional mux or 2-input function generator on outputs

• 12 mA or 24 mA output drive

• 5V and 3.3V PCI compliant

• Enhanced Boundary Scan

• Express Mode configuration

• Chip scale packaging  

 

           

    Spartan-II 2.5V FPGA

 Features

• Second generation ASIC replacement technology

- Densities as high as 5,292 logic cells with up to

200,000 system gates

- Streamlined features based on Virtex architecture

- Unlimited reprogrammability

- Very low cost

- Advanced 0.18 micron process

• System level features

- SelectRAM+™ hierarchical memory:

ท 16 bits/LUT distributed RAM

ท Configurable 4K bit block RAM

ท Fast interfaces to external RAM

- Fully PCI compliant

- Low-power segmented routing architecture

- Full readback ability for verification/observability

- Dedicated carry logic for high-speed arithmetic

- Efficient multiplier support

- Cascade chain for wide-input functions

- Abundant registers/latches with enable, set, reset

- Four dedicated DLLs for advanced clock control

- Four primary low-skew global clock distribution nets

- IEEE 1149.1 compatible boundary scan logic

• Versatile I/O and packaging

- Pb-free package options

- Low-cost packages available in all densities

- Family footprint compatibility in common packages

- 16 high-performance interface standards

- Hot swap Compact PCI friendly

- Zero hold time simplifies system timing

• Fully supported by powerful Xilinx development system

- Foundation ISE Series: Fully integrated software

- Alliance Series: For use with third-party tools

- Fully automatic mapping, placement, and routing  

                             

     

 Xilinx Spartan-IIE 1.8V FPGA

     

Features

• Second generation ASIC replacement technology

- Densities as high as 15,552 logic cells with up to

600,000 system gates

- Streamlined features based on Virtex-E

architecture

- Unlimited in-system reprogrammability

- Very low cost

- Advanced 0.15 micron technology

• System level features

- SelectRAM+™ hierarchical memory:

ท 16 bits/LUT distributed RAM

ท Configurable 4K-bit true dual-port block RAM

ท Fast interfaces to external RAM

- Fully 3.3V PCI compliant to 64 bits at 66 MHz and

CardBus compliant

- Low-power segmented routing architecture

- Dedicated carry logic for high-speed arithmetic

- Efficient multiplier support

- Cascade chain for wide-input functions

- Abundant registers/latches with enable, set, reset

- Four dedicated DLLs for advanced clock control

ท Eliminate clock distribution delay

ท Multiply, divide, or phase shift

- Four primary low-skew global clock distribution nets

- IEEE 1149.1 compatible boundary scan logic

• Versatile I/O and packaging

- Pb-free package options

- Low-cost packages available in all densities

- Family footprint compatibility in common packages

- 19 high-performance interface standards

ท LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL

ท LVDS and LVPECL differential I/O

- Up to 205 differential I/O pairs that can be input,

output, or bidirectional

- Hot swap I/O (CompactPCI friendly)

• Fully supported by powerful Xilinx ISE development

system

- Fully automatic mapping, placement, and routing

- Integrated with design entry and verification tools

- Extensive IP library including DSP functions and

soft processors

     

    10

Xilinx Spartan-3 FPGA

 Features

• Low-cost, high-performance logic solution for high-volume,

consumer-oriented applications

- Densities up to 74,880 logic cells

• SelectIO™ signaling

- Up to 784 I/O pins

- 622 Mb/s data transfer rate per I/O

- 18 single-ended signal standards

- 8 differential I/O standards including LVDS, RSDS

- Termination by Digitally Controlled Impedance

- Signal swing ranging from 1.14V to 3.45V

- Double Data Rate (DDR) support

- DDR, DDR2 SDRAM support up to 333 Mbps

• Logic resources

- Abundant logic cells with shift register capability

- Wide, fast multiplexers

- Fast look-ahead carry logic

- Dedicated 18 x 18 multipliers

- JTAG logic compatible with IEEE 1149.1/1532

• SelectRAM™ hierarchical memory

- Up to 1,872 Kbits of total block RAM

- Up to 520 Kbits of total distributed RAM

• Digital Clock Manager (up to four DCMs)

- Clock skew elimination

- Frequency synthesis

- High resolution phase shifting

• Eight global clock lines and abundant routing

• Fully supported by Xilinx ISE™ and WebPACK™

development systems

• MicroBlaze™ and PicoBlaze™ processor, PCI, PCI

ExpressPIPE Endpoint, and other IP cores

• Pb-free packaging options

• Automotive Spartan-3 XA Family variant

   

 

 Xilinx Spartan-3E FPGA

 

Features

• Very low cost, high-performance logic solution for

high-volume, consumer-oriented applications

• Proven advanced 90-nanometer process technology

• Multi-voltage, multi-standard SelectIO™ interface pins

- Up to 376 I/O pins or 156 differential signal pairs

- LVCMOS, LVTTL, HSTL, and SSTL single-ended

signal standards

- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

- 622+ Mb/s data transfer rate per I/O

- True LVDS, RSDS, mini-LVDS, differential

HSTL/SSTL differential I/O

- Enhanced Double Data Rate (DDR) support

- DDR SDRAM support up to 333 Mb/s

• Abundant, flexible logic resources

- Densities up to 33,192 logic cells, including

optional shift register or distributed RAM support

- Efficient wide multiplexers, wide logic

- Fast look-ahead carry logic

- Enhanced 18 x 18 multipliers with optional pipeline

- IEEE 1149.1/1532 JTAG programming/debug port

• Hierarchical SelectRAM™ memory architecture

- Up to 648 Kbits of fast block RAM

- Up to 231 Kbits of efficient distributed RAM

• Up to eight Digital Clock Managers (DCMs)

- Clock skew elimination (delay locked loop)

- Frequency synthesis, multiplication, division

- High-resolution phase shifting

- Wide frequency range (5 MHz to over 300 MHz)

• Eight global clocks plus eight additional clocks per

each half of device, plus abundant low-skew routing

• Configuration interface to industry-standard PROMs

- Low-cost, space-saving SPI serial Flash PROM

- x8 or x8/x16 parallel NOR Flash PROM

- Low-cost Xilinx Platform Flash with JTAG

• Complete Xilinx ISE™ and WebPACK™ development

system support

• MicroBlaze™ and PicoBlazeembedded processor

cores

• Fully compliant 32-/64-bit 33 MHz PCI support

(66 MHz in some devices)

• Low-cost QFP and BGA packaging options

- Common footprints support easy density migration

- Pb-free packaging options      

   

    XilinxSpartan-3A FPGA  

   

Features

Very low cost, high-performance logic solution for

high-volume, cost-conscious applications

Dual-range VCCAUX supply simplifies 3.3V-only design

Suspend, Hibernate modes reduce system power

Multi-voltage, multi-standard SelectIO™ interface pins

 Up to 502 I/O pins or 227 differential signal pairs

 LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

 Selectable output drive, up to 24 mA per pin

 QUIETIO standard reduces I/O switching noise

 Full 3.3V 10% compatibility and hot swap compliance

 622+ Mb/s data transfer rate per differential I/O

 LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O

with integrated differential termination resistors

 Enhanced Double Data Rate (DDR) support

 DDR/DDR2 SDRAM support up to 333 Mb/s

 Fully compliant 32-/64-bit, 33/66 MHz PCItechnology

support

Abundant, flexible logic resources

 Densities up to 25,344 logic cells, including optional shift

register or distributed RAM support

 Efficient wide multiplexers, wide logic

 Fast look-ahead carry logic

 Enhanced 18 x 18 multipliers with optional pipeline

 IEEE 1149.1/1532 JTAG programming/debug port

Hierarchical SelectRAM™ memory architecture

 Up to 576 Kbits of fast block RAM with byte write enables

for processor applications

 Up to 176 Kbits of efficient distributed RAM

Up to eight Digital Clock Managers (DCMs)

 Clock skew elimination (delay locked loop)

 Frequency synthesis, multiplication, division

 High-resolution phase shifting

 Wide frequency range (5 MHz to over 320 MHz)

Eight low-skew global clock networks, eight additional

clocks per half device, plus abundant low-skew routing

Configuration interface to industry-standard PROMs

 Low-cost, space-saving SPI serial Flash PROM

 x8 or x8/x16 parallel NOR Flash PROM

 Low-cost Xilinx Platform Flash with JTAG

 Unique Device DNA identifier for design authentication

 Load multiple bitstreams under FPGA control

Complete Xilinx ISE™ and WebPACK™ development

system software support plus Spartan-3A Starter Kit

MicroBlaze™ and PicoBlaze embedded processor cores

Low-cost QFP and BGA packaging, Pb-free options

 Common footprints support easy density migration

 Compatible with select Spartan-3AN nonvolatile FPGAs

 Compatible with higher density Spartan-3A DSP FPGAs  

   

Xilinx Spartan-3AN FPGA

 

Features

The new standard for low cost non-volatile FPGA solutions

Eliminates traditional non-volatile FPGA limitations with the

advanced 90 nm Spartan-3A feature set

 Memory, multipliers, DCMs, SelectIO, hot swap, power

management, etc.

Integrated robust configuration memory

 Saves board space

 Improves ease-of-use

 Simplifies design

 Reduces support issues

Plentiful amounts of non-volatile memory available to the user

 Up to 11+ Mb available

 MultiBoot support

 Embedded processing and code shadowing

 Scratchpad memory

Robust 100K Flash memory program/erase cycles

20 years Flash memory data retention

Security features provide bitstream anti-cloning protection

 Buried configuration interface

 Unique Device DNA serial number in each device for

design Authentication to prevent unauthorized copying

 Flash memory sector protection and lockdown

Configuration watchdog timer automatically recovers from

configuration errors

Suspend mode reduces system power consumption

 Retains all design state and FPGA configuration data

 Fast response time, typically less than 100 s

Full hot-swap compliance

Multi-voltage, multi-standard SelectIO™ interface pins

 Up to 502 I/O pins or 227 differential signal pairs

 LVCMOS, LVTTL, HSTL, and SSTL single-ended signal

standards

 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

 Up to 24 mA output drive

 3.3V10% compatibility and hot swap compliance

 622+ Mb/s data transfer rate per I/O

 LVDS, RSDS, mini-LVDS, PPDS, HSTL/SSTL differential

I/O

Abundant, flexible logic resources

 Densities up to 25,344 logic cells

 Optional shift register or distributed RAM support

 Enhanced 18 x 18 multipliers with optional pipeline

Hierarchical SelectRAM™ memory architecture

 Up to 576 Kbits of dedicated block RAM

 Up to 176 Kbits of efficient distributed RAM

Up to eight Digital Clock Managers (DCMs)

Eight global clocks and eight additional clocks per each half

of device, plus abundant low-skew routing

Complete Xilinx ISE™ and WebPACK™ development system

support

MicroBlaze™ and PicoBlaze embedded processor cores

Fully compliant 32-/64-bit 33 MHz PCI support

Low-cost QFP and BGA packaging options

 Pin-compatible with Spartan-3A FPGA family

   

BXilinx Spartan-3A DSP FPGA

 

Features

Very low cost, high-performance DSP solution for

high-volume, cost-conscious applications

250 MHz XtremeDSP DSP48A Slices

 Dedicated 18-bit by 18-bit multiplier

 Available pipeline stages for enhanced performance of at least

250 MHz in the standard -4 speed grade

 48-bit accumulator for multiply-accumulate (MAC) operation

 Integration added for complex multiply or multiply-add operation

 Integrated 18-bit pre-adder

 Optional cascaded Multiply or MAC

Hierarchical SelectRAM™ memory architecture

 Up to 2268 Kbits of fast block RAM with byte write enables for

processor applications

 Up to 373 Kbits of efficient distributed RAM

 Registered outputs on the block RAM with operation of at least

280 MHz in the standard -4 speed grade

Dual-range VCCAUX supply simplifies 3.3V-only design

Suspend, Hibernate modes reduce system power

Low-power option reduces quiescent current

Multi-voltage, multi-standard SelectIO™ interface pins

 Up to 519 I/O pins or 227 differential signal pairs

 LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

 Selectable output drive, up to 24 mA per pin

 QUIETIO standard reduces I/O switching noise

 Full 3.3V 10% compatibility and hot swap compliance

 622+ Mb/s data transfer rate per differential I/O

 LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with

integrated differential termination resistors

 Enhanced Double Data Rate (DDR) support

 DDR/DDR2 SDRAM support up to 333 Mb/s

 Fully compliant 32-/64-bit, 33/66 MHz PCI support

Abundant, flexible logic resources

 Densities up to 53712 logic cells, including optional shift register

 Efficient wide multiplexers, wide logic

 Fast look-ahead carry logic

 IEEE 1149.1/1532 JTAG programming/debug port

Eight Digital Clock Managers (DCMs)

 Clock skew elimination (delay locked loop)

 Frequency synthesis, multiplication, division

 High-resolution phase shifting

 Wide frequency range (5 MHz to over 320 MHz)

Eight low-skew global clock networks, eight additional clocks

per half device, plus abundant low-skew routing

Configuration interface to industry-standard PROMs

 Low-cost, space-saving SPI serial Flash PROM

 x8 or x8/x16 parallel NOR Flash PROM

 Low-cost Xilinx Platform Flash with JTAG

 Unique Device DNA identifier for design authentication

 Load multiple bitstreams under FPGA control

MicroBlaze™ and PicoBlaze™ embedded processor cores

BGA and CSP packaging with Pb-free options  

 

 

Xilinx Virtex 2.5 V FPGA

 

Features

• Fast, high-density Field-Programmable Gate Arrays

- Densities from 50k to 1M system gates

- System performance up to 200 MHz

- 66-MHz PCI Compliant

- Hot-swappable for Compact PCI

• Multi-standard SelectIO™ interfaces

- 16 high-performance interface standards

- Connects directly to ZBTRAM devices

• Built-in clock-management circuitry

- Four dedicated delay-locked loops (DLLs) for

advanced clock control

- Four primary low-skew global clock distribution

nets, plus 24 secondary local clock nets

• Hierarchical memory system

- LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

- Configurable synchronous dual-ported 4k-bit

RAMs

- Fast interfaces to external high-performance RAMs

• Flexible architecture that balances speed and density

- Dedicated carry logic for high-speed arithmetic

- Dedicated multiplier support

- Cascade chain for wide-input functions

- Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

- Internal 3-state bussing

- IEEE 1149.1 boundary-scan logic

- Die-temperature sensor diode

• Supported by FPGA Foundation™ and Alliance

Development Systems

- Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

- Wide selection of PC and workstation platforms

• SRAM-based in-system configuration

- Unlimited re-programmability

- Four programming modes

• 0.22m 5-layer metal process

• 100% factory tested

 

     

Xilinx Virtex-II FPGA

 

• Industry First Platform FPGA Solution

• IP-Immersion Architecture

- Densities from 40K to 8M system gates

- 420 MHz internal clock speed (Advance Data)

- 840+ Mb/s I/O (Advance Data)

• SelectRAM™ Memory Hierarchy

- 3 Mb of dual-port RAM in 18 Kbit block SelectRAM

resources

- Up to 1.5 Mb of distributed SelectRAM resources

• High-Performance Interfaces to External Memory

- DRAM interfaces

ท SDR / DDR SDRAM

ท Network FCRAM

ท Reduced Latency DRAM

- SRAM interfaces

ท SDR / DDR SRAM

ท QDR™ SRAM

- CAM interfaces

• Arithmetic Functions

- Dedicated 18-bit x 18-bit multiplier blocks

- Fast look-ahead carry logic chains

• Flexible Logic Resources

- Up to 93,184 internal registers / latches with Clock

Enable

- Up to 93,184 look-up tables (LUTs) or cascadable

16-bit shift registers

- Wide multiplexers and wide-input function support

- Horizontal cascade chain and sum-of-products

support

- Internal 3-state bussing

• High-Performance Clock Management Circuitry

- Up to 12 DCM (Digital Clock Manager) modules

ท Precise clock de-skew

ท Flexible frequency synthesis

ท High-resolution phase shifting

- 16 global clock multiplexer buffers

• Active Interconnect Technology

- Fourth generation segmented routing structure

- Predictable, fast routing delay, independent of

fanout

 

• SelectIO™-Ultra Technology

- Up to 1,108 user I/Os

- 19 single-ended and six differential standards

- Programmable sink current (2 mA to 24 mA) per I/O

- Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

- PCI-X compatible (133 MHz and 66 MHz) at 3.3V

- PCI compliant (66 MHz and 33 MHz) at 3.3V

- CardBus compliant (33 MHz) at 3.3V

- Differential Signaling

ท 840 Mb/s Low-Voltage Differential Signaling I/O

(LVDS) with current mode drivers

ท Bus LVDS I/O

ท Lightning Data Transport (LDT) I/O with current

driver buffers

ท Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

ท Built-in DDR input and output registers

- Proprietary high-performance SelectLink

Technology

ท High-bandwidth data path

ท Double Data Rate (DDR) link

ท Web-based HDL generation methodology

• Supported by Xilinx Foundation™ and Alliance

Series™ Development Systems

- Integrated VHDL and Verilog design flows

- Compilation of 10M system gates designs

- Internet Team Design (ITD) tool

• SRAM-Based In-System Configuration

- Fast SelectMAP configuration

- Triple Data Encryption Standard (DES) security

option (Bitstream Encryption)

- IEEE 1532 support

- Partial reconfiguration

- Unlimited reprogrammability

- Readback capability

• 0.15 ตm 8-Layer Metal Process with 0.12 ตm

High-Speed Transistors

• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V

VCCAUX Auxiliary and VCCO I/O Power Supplies

• IEEE 1149.1 Compatible Boundary-Scan Logic

Support

• Flip-Chip and Wire-Bond Ball Grid Array (BGA)

100% Factory Tested

 

    XILINX Virtex-II Pro and Virtex-II Pro X  FPGA:

 

Features

• High-Performance Platform FPGA Solution, Including

- Up to twenty RocketIO™ or RocketIO X embedded

Multi-Gigabit Transceivers (MGTs)

- Up to two IBM PowerPC™ RISC processor blocks

• Based on Virtex-II™ Platform FPGA Technology

- Flexible logic resources

- SRAM-based in-system configuration

- Active Interconnect technology

- SelectRAM™+ memory hierarchy

- Dedicated 18-bit x 18-bit multiplier blocks

- High-performance clock management circuitry

- SelectI/O™-Ultra technology

- XCITE Digitally Controlled Impedance (DCI) I/O

Virtex-II Pro / Virtex-II Pro X family members and resources

are shown in Table 1.

• Variable-Speed Full-Duplex Transceiver (XC2VPX20)

Allowing 2.488 Gb/s to 6.25 Gb/s Baud Transfer Rates.

- Includes specific baud rates used by various

standards, as listed in Table 4, Module 2.

• Fixed-Speed Full-Duplex Tranceiver (XC2VPX70)

Operating at 4.25 Gb/s Baud Transfer Rate.

• Eight or Twenty Transceiver Modules on an FPGA,

Depending upon Device

• Monolithic Clock Synthesis and Clock Recovery

- Eliminates the need for external components

 

   

QPro Virtex-II 1.5V Radiation-Hardened

QML Platform FPGA 

   

Hardened QPro™ Virtex-II Features

• Industry First Radiation Hardened Platform FPGA

Solution

• Guaranteed total ionizing dose to 200K Rad(Si)

• Latch-up immune to LET > 160 MeV-cm2/mg

• SEU in GEO upsets < 1.5E-6 per device day achievable

with recommended redundancy implementation

• Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

• Guaranteed over the full military temperature range

(–55C to +125C)

• 0.15 ตm 8-Layer Metal Process with 0.12 ตm

High-Speed Transistors

• Ceramic and Plastic Wire-Bond and Flip-Chip Grid

Array Packages

• IP-Immersion Architecture

 Densities from 1M to 6M system gates

 300+ MHz internal clock speed (Advance Data)

 622+ Mb/s I/O (Advance Data)

• SelectRAM™ Memory Hierarchy

 2.5 Mb of dual-port RAM in 18 Kbit block

SelectRAM resources

 Up to 1 Mb of distributed SelectRAM resources

• High-Performance Interfaces to External Memory

 DRAM interfaces

- SDR/DDR SDRAM

- Network FCRAM

- Reduced Latency DRAM

 SRAM interfaces

- SDR/DDR SRAM

- QDR SRAM

 CAM interfaces

• Arithmetic Functions

 Dedicated 18-bit x 18-bit multiplier blocks

 Fast look-ahead carry logic chains

• Flexible Logic Resources

 Up to 67,584 internal registers/latches with Clock

Enable

 Up to 67,584 look-up tables (LUTs) or cascadable

16-bit shift registers

 Wide multiplexers and wide-input function support

 Horizontal cascade chain and sum-of-products

support

 Internal 3-state busing

 

• High-Performance Clock Management Circuitry

 Up to 12 DCM (Digital Clock Manager) modules

- Precise clock de-skew

- Flexible frequency synthesis

- High-resolution phase shifting

 16 global clock multiplexer buffers

• Active Interconnect Technology

 Fourth generation segmented routing structure

 Predictable, fast routing delay, independent of fanout

• SelectIO™-Ultra Technology

 Up to 824 user I/Os

 19 single-ended and six differential standards

 Programmable sink current (2 mA to 24 mA) per

I/O

 Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

 Differential Signaling

- 622 Mb/s Low-Voltage Differential Signaling

I/O (LVDS) with current mode drivers

- Bus LVDS I/O

- Lightning Data Transport (LDT) I/O with current

driver buffers

- Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

- Built-in DDR input and output registers

 Proprietary high-performance SelectLink Technology

- High-bandwidth data path

- Double Data Rate (DDR) link

- Web-based HDL generation methodology

• Supported by Xilinx Foundation Series™ and Alliance

Series™ Development Systems

 Integrated VHDL and Verilog design flows

 Compilation of 10M system gates designs

 Internet Team Design (ITD) tool

• SRAM-Based In-System Configuration

 Fast SelectMAP configuration

 IEEE 1532 support

 Partial reconfiguration

 Unlimited reprogrammability

 Readback capability

• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V

VCCAUX Auxiliary and VCCO I/O Power Supplies

• IEEE 1149.1 Compatible Boundary-Scan Logic Support

 

 XILINX Virtex-4 FPGA

 

Virtex-4 Family Features

• Three Families — LX/SX/FX

- Virtex-4 LX: High-performance logic applications solution

- Virtex-4 SX: High-performance solution for digital signal

processing (DSP) applications

- Virtex-4 FX: High-performance, full-featured solution for

embedded platform applications

• Xesium™ Clock Technology

- Digital clock manager (DCM) blocks

- Additional phase-matched clock dividers (PMCD)

- Differential global clocks

• XtremeDSP™ Slice

- 18 x 18, two’s complement, signed Multiplier

- Optional pipeline stages

- Built-in Accumulator (48-bit) and Adder/Subtracter

• Smart RAM Memory Hierarchy

- Distributed RAM

- Dual-port 18-Kbit RAM blocks

ท Optional pipeline stages

ท Optional programmable FIFO logic automatically

remaps RAM signals as FIFO signals

- High-speed memory interface supports DDR and DDR-2

SDRAM, QDR-II, and RLDRAM-II.

• SelectIO™ Technology

- 1.5V to 3.3V I/O operation

- Built-in ChipSync™ source-synchronous technology

- Digitally controlled impedance (DCI) active termination

- Fine grained I/O banking (configuration in one bank)

• Flexible Logic Resources

• Secure Chip AES Bitstream Encryption

• 90-nm Copper CMOS Process

• 1.2V Core Voltage

• Flip-Chip Packaging including Pb-Free Package

Choices

• RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit

Transceiver (MGT) [FX only]

• IBM PowerPC RISC Processor Core [FX only]

- PowerPC 405 (PPC405) Core

- Auxiliary Processor Unit Interface (User Coprocessor)

• Multiple Tri-Mode Ethernet MACs [FX only]

 

  Xilinx Virtex-5 FPGA

 

Summary of Virtex-5 Features

• Four platforms LX, LXT, SXT, and FXT

- Virtex-5 LX: High-performance general logic applications

- Virtex-5 LXT: High-performance logic with advanced

serial connectivity

- Virtex-5 SXT: High-performance signal processing

applications

- Virtex-5 FXT: High-performance embedded systems

• Cross-platform compatibility

- LXT, SXT, and FXT devices are footprint compatible in

the same package

• Most advanced, high-performance, optimal-utilization,

FPGA fabric

- Real 6-input look-up table (LUT) technology

- Dual 5-LUT option

- Improved reduced-hop routing

- 64-bit distributed RAM option

- SRL32/Dual SRL16 option

• Powerful clock management tile (CMT) clocking

- Digital Clock Manager (DCM) blocks for zero delay

buffering, frequency synthesis, and clock phase shifting

- PLL blocks for input jitter filtering, zero delay buffering,

frequency synthesis, and phase-matched clock division

• 36-Kbit block RAM/FIFOs

- True dual-port RAM blocks

- Enhanced optional programmable FIFO logic

- Programmable

ท True dual-port widths up to x36

ท Simple dual-port widths up to x72

- Built-in optional error-correction circuitry

- Optionally program each block as two independent

18-Kbit blocks

• 65-nm copper CMOS process technology

• 1.0V core voltage

• High signal-integrity flip-chip packaging available in

standard or Pb-free package options

 

• High-performance parallel SelectIO technology

- 1.2 to 3.3V I/O Operation

- Source-synchronous interfacing using ChipSync

technology

- Digitally-controlled impedance (DCI) active termination

- Flexible fine-grained I/O banking

- High-speed memory interface support

• Advanced DSP48E slices

- 25 x 18, two’s complement, multiplication

- Optional adder, subtracter, and accumulator

- Optional pipelining

- Optional bitwise logical functionality

- Dedicated cascade connections

• Flexible configuration options

- SPI and Parallel FLASH interface

- Multi-bitstream support with dedicated fallback

reconfiguration logic

- Auto bus width detection capability

• Integrated Endpoint blocks for PCI Express (LXT/SXT)

- Compliant with the PCI Express Base Specification 1.1

- x1, x2, x4, or x8 lane support per block

- Works in conjunction with RocketIO™ transceivers

• Tri-mode 10/100/1000 Mb/s Ethernet MACs

(LXT/SXT)

- RocketIO transceivers can be used as PHY or connect to

external PHY using many soft MII (Media Independent

Interface) options

• RocketIO GTP transceivers 100 Mb/s to 3.2 Gb/s

(LXT/SXT)

• System Monitoring capability on all devices

- On-chip/Off-chip thermal monitoring

- On-chip/Off-chip power supply monitoring

- JTAG access to all monitored quantities

 

Xilinx XC9500XV Family

High-Performance CPLD 

   

Features

• Optimized for high-performance 2.5V systems

- 5 ns pin-to-pin logic delays

- Small footprint packages including VQFPs, TQFPs

and CSPs (Chip Scale Package)

- Lower power operation

- Multi-voltage operation

- FastFLASH technology

• Advanced system features

- In-system programmable

- Output banking (XC95144XV, XC95288XV)

- Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with

individual product-term allocation

- Local clock inversion with three global and one

product-term clocks

- Individual output enable per output pin with local

inversion

- Input hysteresis on all user and boundary-scan pin

inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

support on all devices

• Four pin-compatible device densities

- 36 to 288 macrocells, with 800 to 6400 usable

gates

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- 20 year data retention

- ESD protection exceeding 2,000V

• Pin-compatible with 3.3V core XC9500XL family in

common package footprints

• Hot Plugging capability

       

Xilinx CoolRunner-II CPLD   

 

Features

• Optimized for 1.8V systems

- Industry’s fastest low power CPLD

- Densities from 32 to 512 macrocells

• Industry’s best 0.18 micron CMOS CPLD

- Optimized architecture for effective logic synthesis

- Multi-voltage I/O operation — 1.5V to 3.3V

• Advanced system features

- Fastest in system programming

ท 1.8V ISP using IEEE 1532 (JTAG) interface

- On-The-Fly Reconfiguration (OTF)

- IEEE1149.1 JTAG Boundary Scan Test

- Optional Schmitt trigger input (per pin)

- Multiple I/O banks on all devices

- Unsurpassed low power management

DataGATE external signal control

- Flexible clocking modes

ท Optional DualEDGE triggered registers

ท Clock divider (2,4,6,8,10,12,14,16)

CoolCLOCK

- Global signal options with macrocell control

ท Multiple global clocks with phase selection per

macrocell

ท Multiple global output enables

ท Global set/reset

- Abundant product term clocks, output enables and

set/resets

- Efficient control term clocks, output enables and

set/resets for each macrocell and shared across

function blocks

- Advanced design security

- Open-drain output option for Wired-OR and LED

drive

- Optional bus-hold, 3-state or weak pullup on select

I/O pins

- Optional configurable grounds on unused I/Os

- Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels on all parts

- SSTL2_1,SSTL3_1, and HSTL_1 on 128

macrocell and denser devices

- Hot pluggable

• PLA architecture

- Superior pinout retention

- 100% product term routability across function block

 Wide package availability including fine pitch:

- Chip Scale Package (CSP) BGA, Fine Line BGA,

TQFP, PQFP, VQFP, PLCC, and QFN packages

- Pb-free available for all packages

• Design entry/verification using Xilinx and industry

standard CAE tools

• Free software support for all densities using Xilinx

WebPACK™

• Industry leading nonvolatile 0.18 micron CMOS

process

- Guaranteed 1,000 program/erase cycles

- Guaranteed 20 year data retention


Home