WISHBONE Conmax IP Core: Overview

project properties Category ::SoC Language::Verilog Standard::Wishbone compliant core Development status :: Stable

Description

This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves

Some of the main features are:

• Up to 8 Masters
• Up to 16 Slaves
• 1, 2 or 4 priority levels
• Fully configurable

Example SoC with the CONMAX IP Core

This IP Core is provided by:

www.ASICS.ws - Solutions for your ASIC/FPGA needs -

Verilog Source Code ,Test Bench & Documentation

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